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1 article(s) from Hassan, Jumiah

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

Farhad Larki,
Arash Dehzangi,
Alam Abedini,
Ahmad Makarimi Abdullah,
Elias Saion,
Sabar D. Hutagalung,
Mohd N. Hamidon and
Jumiah Hassan

Beilstein J. Nanotechnol. 2012, 3, 817–823, doi:10.3762/bjnano.3.91

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Figure 1: (a) AFM topographic images depicting a series of oxide protrusions produced by applying various vol...

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Figure 2: AFM topography image of the final structure.

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Figure 3: (a) Isometric view of the simulated device. (b) Blow up view of the gated area and different nanowi...

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Figure 4: (a) SEM image of the gated area. (b) Experimental measurement and simulated transfer characteristic...

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Figure 5: Hole concentration for a vertical cut of DGJLT at (X = −100 nm) for four different gate voltages (a...

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Figure 6: (a) Hole density and (b) electron density distribution as a function of position along a horizontal...

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Figure 7: Simulated (a) parallel and (b) normal electric field along a horizontal cut line at the center of t...

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Full Research Paper

Published 03 Dec 2012

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